The present invention relates to an analog front-end (AFE) for an imaging sensor, and in particular to a correlated double sampler (CDS), programmable gain amplifier (PGA), and sample and hold circuit (S/H) for CCD signal digitization.
Imaging systems which may support a CCD sensor or a CMOS sensor typically require an AFE chip which samples the analog signal under control of a timing generator. Typically, a voltage amplifier is used. The sampled signal is then amplified and provided to a separate chip for digitization and subsequent processing.
Typically, a black reference level is sampled immediately before every pixel of a video signal. These two values are then separately provided to the digital processing circuitry. Related prior art is described below:
U.S. Pat. No. 5,796,361. This patent describes a single chip, cost effective implementation of a CCD signal digitizing circuit which uses a standard technique to correct for the pixel-to-pixel variation of the black reference level.
U.S. Pat. No. 4,287,441. This patent describes a high speed correlated double sampling amplifier.
U.S. Pat. No. 5,703,524. This Exar patent describes a Piece-Wise Linear Approximation of a DB linear Programmable Gain Amplifier.
U.S. Pat. No. 6,018,269. This Texas Instruments, Inc. patent shows a Programmable Gain Amplifier with transimpedance and transconductance amplifiers.
U.S. Pat. No. 6,025,875. This National Semiconductor patent shows an Analog Signal Sampler for Imaging Systems.